A frame of displays, such as a liquid crystal display (hereinafter “LCD”), an electroluminescent display, or an organic light emitting diode display, etc, is generated by a plurality of pixels of matrices. Thus, sequential pulses are basic signals driving the display. In addition, the sequential pulses are generated by a shift register circuit, so the shift register circuit becomes a general unit for the driving circuit of a display.
FIG. 11 shows a conventional shift-register circuit as disclosed by U.S. Pat. No. 5,434,899, issued to Huq et al. In shift register 1100 of FIG. 11(a), stages n−1, n, n+1 and n+2 are coupled to one another in a cascade configuration. An output signal of a given stage is coupled to an input of the immediately subsequent stage in the cascade configuration. For example, an output pulse OUTn−1 of a preceding stage n−1 in the cascade configuration of register 1100 is coupled to an input terminal 12 of stage n of the detail shift register circuit as shown in FIG. 11(b). Illustratively, only four stages, n−1, n, n+1 and n+2 are shown. However, the total number of stages n in the cascade configuration of the register 1100 is substantially larger. A clock generator 1101 of FIG. 11(a) generates a three-phase clock signal C1, C2 and C3 as shown in FIG. 12.
As illustrated in FIGS. 11 and 12, the pulse of signal OUTn−1 of FIG. 11(a) is produced when the pulse of clock signal C3 is applied to stage n−1. Signal OUTn−1 of FIG. 11(b) is developed at an input terminal 12 of stage n. Signal OUTn−1 at the HIGH voltage level is coupled via transistor 18 operating as a switch to a terminal 18a for developing a control signal P1. Signal P1 at the HIGH voltage level is temporarily stored in an inter-electrode capacitance, not shown, and in a capacitor CB. Signal P1 that is developed at the gate of an output transistor 16 of FIG. 11(b) conditions output transistor 16 for conduction. When clock signal C1 occurs, signal C1 that is developed at a terminal 14 of FIG. 11(b) or source electrode of transistor 16 is coupled via an inter-electrode capacitance CP in phantom and capacitance CB to the gate electrode of transistor 16, or terminal 18a, for turning on the conditioned transistor 16. Consequently, an output pulse signal OUTn is developed at a drain terminal 13. Signal OUTn is applied to the input of subsequent stage n+1 of FIG. 11(a). Stage n+1 operates similarly to stage n except for utilizing clock signal C2, instead of clock signal C1 in stage n, for turning on the corresponding transistor.
A transistor 25 has its drain-source conduction path coupled between terminal 18a and a point of reference potential sufficient to turn pull-up transistor 16 off when the transistor 25 is conductive. The gate of the transistor 25 is coupled to an output of subsequent stage n+2 in the chain as shown in FIG. 11(a) and is controlled by an output signal OUTn+2.
However, such a conventional shift register stage is enabled by the output signal of the prior stage and is disabled either by a control signal or by the output signal of a subsequent stage. The first disable method costs one applied signal source. The second disable method has cross stage connection wiring. In the conventional shift register circuit discussed above, the dynamic shift register stage n is disabled by a shift register stage after the next, i.e., shift register stage n+2. The circuit layout of the conventional shift register circuit is complicated by the additional required feedback. The cross stage wiring may also cause instability of the shift register circuitry.
Therefore, a heretofore unaddressed need exists in the art to address the aforementioned deficiencies and inadequacies.